爱华网以低电平输出为例：
第一种：case语句
`timescale 10ns/1ns
module decode3_8(data_out,data_in,enable) ;
input [2:0] data_in;
input enable;
output [7:0] data_out;
reg [7:0] data_out;
always @(data_in orenable)
begin
if (enable==1)
case (data_in )
3'b000: data_out=8'b11111110;
3'b001: data_out=8'b11111101;
3'b010: data_out=8'b11111011;
3'b011: data_out=8'b11110111;
3'b100: data_out=8'b11101111;
3'b101: data_out=8'b11011111;
3'b110: data_out=8'b10111111;
3'b111: data_out=8'b01111111;
default: data_out=8'bxxxxxxxx;
endcase
else
data_out=8'b11111111;
end
endmodule
第二种：if-else if语句
`timescale 10ns/1ns
module decode3_8(data_out,data_in,enable) ;
input [2:0] data_in;
input enable;
output [7:0] data_out;
reg [7:0] data_out;
always @(data_in orenable)
begin
if (enable==1)
if(data_in==3'b000)
data_out=8'b11111110;
else if(data_in==3'b001)
data_out=8'b11111101;
else if(data_in==3'b010)
data_out=8'b11111011;
else if(data_in==3'b011)
data_out=8'b11110111;
else if(data_in==3'b100)
data_out=8'b11101111;
else if(data_in==3'b101)
data_out=8'b11011111;
else if(data_in==3'b110)
data_out=8'b10111111;
else if(data_in==3'b111)
data_out=8'b01111111;
else
data_out=8'bxxxxxxxx;
else
data_out = 8'b11111111;
end
endmodule
第三种：算法实现，但是不可综合
`timescale 10ns/1ns
module decode3_8(data_out,data_in,enable) ;
input [2:0] data_in;
input enable;
output [7:0] data_out;
reg A=8’b0000_0001;
assigndata_out=(enable)?(~(A<<data_in-1)):8'b1111_1111;
endmodule
第四种：for语句（1）
`timescale 10ns/1ns
module decode3_8(data_out,data_in,enable) ;
input [2:0] data_in;
input enable;
output [7:0] data_out;
reg [7:0] data_out;
integer i;
always @(data_in orenable)
begin
if(enable)
begin
for(i=0;i<8;i=i+1)
begin
if(data_in==i)
data_out[i]=0;
else
data_out[i]=1;
end
end
else
data_out=8'hff;
end
endmodule
第五种：带条件的连续赋值
`timescale 10ns/1ns
module decode3_8(data_out,data_in,enable) ;
input [2:0] data_in;
input enable;
output [7:0] data_out;
assign data_out =
({enable,data_in}==4'b1000)?8'b1111_1110:
({enable,data_in}==4'b1001)?8'b1111_1101:
({enable,data_in}==4'b1010)?8'b1111_1011:
({enable,data_in}==4'b1011)?8'b1111_0111:
({enable,data_in}==4'b1100)?8'b1110_1111:
({enable,data_in}==4'b1101)?8'b1101_1111:
({enable,data_in}==4'b1110)?8'b1011_1111:
({enable,data_in}==4'b1111)?8'b0111_1111:
8'b1111_1111;
endmodule
第六种：for语句（2）
`timescale 10ns/1ns
module decode3_8(data_out,data_in,enable) ;
input [2:0] data_in;
input enable;
output [7:0] data_out;
reg [7:0] data_out;
integer i;
always @(data_in orenable)
begin
data_out=8'hff;
if(enable)
begin
for(i=0;i<8;i=i+1)
begin
if(data_in==i)
data_out =255-(1<<i);
end
end
else
data_out=8'hff;
end
endmodule
Testbench写法：
以使用Cadence的Ncverilog和Simvision工具为例来说明：
`timescale 10ns/1ns
module decode3_8_tb;
reg[2:0]data_in_tb;
wire [7:0]data_out_tb;
regenable_tb;
decode3_8 decode3_8(.data_in(data_in_tb),.data_out (data_out_tb ),.enable(enable_tb));
initial
begin
$shm_open(“tb.shm”);
$shm_probe(“AC”);
enable_tb=0;
data_in_tb=0;
#20 enable_tb=1;
#50 data_in_tb =0;
#50 data_in_tb=1;
#50 data_in_tb=2;
#50 data_in_tb=3;
#50 data_in_tb=4;
#50 data_in_tb=5;
#50 data_in_tb=6;
#50 data_in_tb=7;
$finish();
end
endmodule
